Title :
A BIST approach for very deep sub-micron (VDSM) defects
Author :
Sato, Yasuo ; Ikeya, Toyohto ; Nakao, Michinobu ; Nagumo, Takaharu
Author_Institution :
Device Dev. Center, Hitachi Ltd., Ome, Japan
Abstract :
This paper presents a BIST approach for the very deep submicron (VDSM) defects in an ASIC. As bridging or open defects are dominant in VDSM, efficient and accurate tests to detect them are now strongly required. We evaluated the BIST patterns for various criteria. These evaluations and additional real chip experiments have indicated that BIST has better detectability of defects than the conventional stored test
Keywords :
application specific integrated circuits; built-in self test; design for testability; fault simulation; integrated circuit design; integrated circuit testing; logic testing; ASIC; BIST approach; BIST patterns; bridging defects; defect detectability; open defects; very deep submicron defects; Application specific integrated circuits; Automatic testing; Bridges; Built-in self-test; Costs; Electronic equipment testing; Flip-flops; Laboratories; Pins; Timing;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894216
