DocumentCode :
2762252
Title :
Static property checking using ATPG vs. BDD techniques
Author :
Huang, Chung-Yang Ric ; Yang, Bwolen ; Tsai, Huan-Chih ; Cheng, Kwang-Ting Tim
Author_Institution :
California Univ., Santa Barbara, CA, USA
fYear :
2000
fDate :
2000
Firstpage :
309
Lastpage :
316
Abstract :
Static property checking verifies pre-defined functional design rules such as “bus contention”, “racing condition”; and “don´t-care case”. A static property checker typically uses formal verification techniques to prove the property under verification. If the property is proven false, a counter-example is generated for debugging the design. Among the different static property checking approaches, ATPG-based and BDD-based are the most powerful and successful ones. We implement both approaches with several optimization techniques on the same framework to compare their performance. The experimental results on industrial designs show that these two approaches have different strength and weakness in proving the static properties. Furthermore, the results indicate that they often complement each other and therefore a hybrid approach may result in better performance. We propose a static property checker based on combined ATPG and BDD techniques. The experimental results show that this combined approach can prove all the static properties in the test cases while still maintaining comparable performance
Keywords :
Boolean functions; automatic test pattern generation; binary decision diagrams; circuit optimisation; formal verification; integrated circuit design; integrated circuit testing; logic CAD; logic testing; tree searching; BDD techniques; Boolean functions; CAD; branch-and-bound algorithms; bus contention; comparable performance; conflict analysis; data representation; design debugging; don´t-care case; formal verification; hybrid approach; optimization techniques; predefined functional design rules; racing condition; static property checking; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Data structures; Debugging; Discrete event simulation; Formal verification; Logic; Natural languages; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
ISSN :
1089-3539
Print_ISBN :
0-7803-6546-1
Type :
conf
DOI :
10.1109/TEST.2000.894219
Filename :
894219
Link To Document :
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