On validating data hold times for flip-flops in sequential circuits

Author

Reddy, Sudhakar M. ; Pomeranz, Irith ; Kajihara, Seiji ; Murakami, Atsushi ; Takeoka, Sadami ; Ohta, Mitsuyasu

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA

fYear

2000

fDate

2000

Firstpage

317

Lastpage

325

Abstract

We consider the problem of validating flip-flop data hold time requirements in sequential circuits. The data hold time violations considered are related to the presence of short paths that allow changes in next-state values to occur fast enough so as to cause latching of erroneous next-states. Three fault models are proposed that are related to the presence of short paths in the circuit. Propagation conditions for robust and non-robust tests for short paths are given. A test generation procedure is described for one of the proposed models, and experimental results are provided for benchmark circuits

Keywords

automatic test pattern generation; boundary scan testing; fault simulation; flip-flops; logic testing; sequential circuits; timing; benchmark circuits; data hold time validation; erroneous next-states; fault models; flip-flop data hold time; full scan; hold time violations; latching; next-state value changes; non-robust tests; propagation conditions; robust tests; sequential circuits; short paths; state transitions; test generation procedure; timing diagram; Circuit faults; Circuit testing; Cities and towns; Clocks; Data engineering; Delay; Flip-flops; Latches; Sequential circuits; Virtual manufacturing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894220

Filename

894220