Title :
Stuck-fault tests vs. actual defects
Author :
Mccluskey, Elisabet J. ; Tseng, Chao-Wen
Author_Institution :
Center for Reliable Comput., Stanford Univ., CA, USA
Abstract :
This paper studies some manufacturing test data collected for an experimental digital IC. Test results for a large variety of single-stuck fault based test sets are shown and compared with a number of test sets based on other fault models. The defects present in the chips studied are characterized based on the chip tester responses. The data presented shows that N-detect test sets are particularly effective for both timing and hard failures. In these test sets each single-stuck fault is detected by at least N different test patterns. We also present data on the use of IDDq tests and VLV (very low voltage) tests for detecting defects whose presence doesn´t interfere with normal operation during manufacturing test, but which cause early life failure
Keywords :
automatic test pattern generation; fault simulation; integrated circuit testing; integrated logic circuits; logic testing; production testing; timing; ATE response; ATPG; IDDq tests; Murphy chip; N-detect test sets; actual defects; chip tester responses; digital IC; fault models; hard failures; manufacturing test data; production defects; reliability defects; single-stuck fault; stuck-fault tests; timing failures; very low voltage tests; Automatic testing; Circuit faults; Circuit testing; Integrated circuit modeling; Integrated circuit testing; Large scale integration; Life testing; Logic testing; Manufacturing; Packaging;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894222
