Optimal INL/DNL testing of A/D converters using a linear model

As Analog to Digital Converters continue to improve in resolution, their linearity testing has become increasingly challenging in terms of test accuracy and test time. In this paper we present a technique for estimation the linearity metrics of an ADC that is optimal in terms of expected r.m.s error in INL/DNL estimates, for a given test time. Experimental results measured on an ADC from industry to validate the effectiveness of the technique are presented