DocumentCode :
2762363
Title :
Optimal analog trim techniques for improving the linearity of pipeline ADCs
Author :
Kuyel, Turker ; Tsay, Frank
Author_Institution :
Texas Instrum. Inc., USA
fYear :
2000
fDate :
2000
Firstpage :
367
Lastpage :
375
Abstract :
This paper investigates the issue of capacitor trimming to improve the linearity of pipeline ADCs that use switched capacitor sub-DACs. Capacitor mismatches create linearity errors, which deteriorate THD, SINAD and SFDR performance of the ADC in communication applications. Measurement of capacitor mismatches and generation of trim capacitor values are discussed. The derivations are for 2-bit-per-stage pipeline ADC architectures and they can easily be extended for any pipelined ADC. Finally, the effectiveness of the overall capacitor trimming process in terms of cost and performance is analyzed for a 12 bit 40 MSPS ADC
Keywords :
analogue-digital conversion; errors; monolithic integrated circuits; pipeline processing; switched capacitor networks; 12 bit; 2-bit-per-stage ADC architectures; A/D convertor linearity; SFDR performance; SINAD performance; THD performance; capacitor mismatches; capacitor trimming; communication applications; linearity errors; optimal analog trim techniques; pipeline ADC architectures; pipeline ADCs; switched capacitor sub-DACs; Capacitors; Error correction; Instruments; Linearity; Pipelines; Production; Resistors; Sampling methods; Testing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
ISSN :
1089-3539
Print_ISBN :
0-7803-6546-1
Type :
conf
DOI :
10.1109/TEST.2000.894226
Filename :
894226
Link To Document :
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