Title :
Selection of potentially testable path delay faults for test generation
Author :
Murakami, Atsushi ; Kajihara, Seiji ; Sasao, Tsutomu ; Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Fac. of Comput. Sci. & Electron., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
We present a method of path selection and test generation for path delay faults. The proposed method addresses the fact that logic circuits typically have very large numbers of paths, and a large percentage of these paths are typically untestable. The proposed method selects a set of potentially testable long paths by utilizing non-enumerative identification of untestable paths and removing untestable paths from consideration. Test generation is also applied as part of the proposed method. We demonstrate the effectiveness of the method by presenting results for benchmark circuits
Keywords :
VLSI; automatic testing; delays; fault location; integrated circuit testing; integrated logic circuits; logic testing; timing; logic circuits; nonenumerative identification; path selection; potentially testable long paths; test generation; testable path delay faults; timing behaviour testing; untestable paths removal; Benchmark testing; Circuit faults; Circuit testing; Cities and towns; Delay; Logic circuits; Logic testing; Performance evaluation; Timing; Very large scale integration;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894227
