Title :
Reconfigurable latch controllers for low power asynchronous circuits
Author :
Lewis, M. ; Garside, J. ; Brackenbury, L.
Author_Institution :
Dept. of Comput. Sci., Manchester Univ., UK
Abstract :
A method for reducing the power consumption in asynchronous micropipeline-based circuits is presented. The method is based around a design for latch controllers in which the operating mode of the pipeline latches (normally open/transparent or normally closed/opaque) can be selected according to the dynamic processing demand on the circuit. Operating in normally-closed mode prevents spurious transitions from propagating along a static pipeline, at the expense of reduced throughput. Tests of the new latch controller circuits on a pipelined multiplier datapath show that reductions in energy per operation of up to 32% can be obtained by changing to the normally-closed operating mode. Estimates suggest that in a typical application which exhibits a variable processing demand, a power reduction of between 16-24% is possible, with little or no impact on maximum throughput
Keywords :
asynchronous circuits; flip-flops; dynamic processing demand; energy per operation; low power asynchronous circuits; maximum throughput; normally-closed operating mode; operating mode; pipelined multiplier datapath; power consumption; reconfigurable latch controllers; static pipeline; variable processing demand; Asynchronous circuits; Communication system control; Computer science; Delay; Latches; Logic circuits; Pipelines; Protocols; Signal processing; Timing;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
0-7695-0031-5
DOI :
10.1109/ASYNC.1999.761520