RAPPID: an asynchronous instruction length decoder

Author

Rotem, Shai ; Stevens, Ken ; Ginosar, Ran ; Beerel, Peter ; Myers, Chris ; Yun, Kenneth ; Kol, Rakefet ; Dike, Charles ; Roncken, Marly ; Agapiev, Boris

Author_Institution

Strategic CAD Lab., Intel Corp., Hillsboro, OR, USA

fYear

1999

fDate

1999

Firstpage

60

Lastpage

70

Abstract

This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID (“Revolving Asynchronous Pentium(R) Processor Instruction Decoder”), a prototype IA32 instruction length decoding and steering unit, was implemented using self-timed techniques. RAPPID chip was fabricated on a 0.25 μ CMOS process and tested successfully. Results show significant advantages-in particular, performance of 2.5-4.5 instructions/nS-with manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400 MHz clocked circuit

Keywords

asynchronous circuits; circuit CAD; high-speed integrated circuits; integrated circuit design; logic CAD; low-power electronics; microprocessor chips; timing; CMOS process; IA32 instruction length; RAPPID; asynchronous design methodology; asynchronous instruction length decoder; latency; revolving asynchronous Pentium processor instruction decoder; self-timed techniques; steering unit; throughput; CMOS process; CMOS technology; Circuit testing; Decoding; Delay; Design methodology; Prototypes; Risk management; Technology management; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on

Conference_Location

Barcelona

ISSN

1522-8681

Print_ISBN

0-7695-0031-5

Type

conf

DOI

10.1109/ASYNC.1999.761523

Filename

761523