Metastability analysis OF CMOS current mode logic latches

Author

Usama, Muhammad ; Kwasniewski, Tad A.

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont.

fYear

2005

fDate

1-4 May 2005

Firstpage

1521

Lastpage

1524

Abstract

This paper presents a detailed analysis of metastable behavior in CMOS current mode logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flip-flop structures. 0.18 mum CMOS technology examples are provided

Keywords

CMOS logic circuits; clocks; current-mode logic; flip-flops; 0.18 mum; CMOS current mode logic latches; clock signal; finite current transition time; flip-flop structures; latch delay; metastability analysis; signal slew rates; CMOS logic circuits; CMOS technology; Clocks; Delay effects; Frequency; Latches; Metastasis; Sampling methods; Signal analysis; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2005. Canadian Conference on

Conference_Location

Saskatoon, Sask.

ISSN

0840-7789

Print_ISBN

0-7803-8885-2

Type

conf

DOI

10.1109/CCECE.2005.1557269

Filename

1557269

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2762660