Precise test generation for resistive bridging faults of CMOS combinational circuits

In this paper we propose a new method to detect resistive bridging faults by logic testing considering fault effects that depend on the gate threshold voltage and gate input vectors. First we show that some bridging faults can be missed to be detected by the traditional test generation method which generates O and 1 at the bridging signal lines, and then propose a novel method to detect resistive bridging faults by logic testing method, which is complete in the sense that the undetectable resistive bridging fault by this algorithm gives correct result in logical operation. A heuristic method using a random pattern has also been proposed for experimental purpose. In order to show the effectiveness of the proposed method some experimental results for benchmark circuits have been shown