• DocumentCode
    2762716
  • Title

    Timed trace theoretic verification using partial order reduction

  • Author

    Yoneda, Tomohiro ; Ryu, Hiroshi

  • Author_Institution
    Dept. of Comput. Sci., Tokyo Inst. of Technol., Japan
  • fYear
    1999
  • fDate
    1999
  • Firstpage
    108
  • Lastpage
    121
  • Abstract
    In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently
  • Keywords
    Petri nets; asynchronous circuits; circuit analysis computing; formal verification; set theory; timing; STARI circuits; Stubborn set method; partial order reduction algorithm; time Petri nets; timed asynchronous circuits; timed specification; timed trace theoretic verification; timing analysis; Clocks; Petri nets;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on
  • Conference_Location
    Barcelona
  • ISSN
    1522-8681
  • Print_ISBN
    0-7695-0031-5
  • Type

    conf

  • DOI
    10.1109/ASYNC.1999.761527
  • Filename
    761527
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2762716