Title :
Exploiting don´t cares to enhance functional tests
Author :
Weiss, Mark W. ; Seth, Sharad C. ; Mehta, Shashank K. ; Einspahr, Kent L.
Author_Institution :
Nebraska-Lincoln Univ., Lincoln, NE, USA
Abstract :
In simulation based design verification, deterministic or pseudo-random tests are used to check functional correctness of a design. In this paper we present a technique generating tests by specifying the don´t care inputs in the functional specifications so as to improve their coverage of both design errors and manufacturing faults. The don´t cares are chosen to maximize sensitization of signals in the circuit. The tests generated in this way require only a fraction of pseudo-exhaustive test patterns to achieve a high multiplicity of fault coverage
Keywords :
automatic test pattern generation; fault simulation; finite state machines; logic simulation; logic testing; border gate identification; design errors; don´t care inputs; fault list generation; functional correctness; functional specifications; functional tests enhancement; high fault coverage multiplicity; logic simulation; manufacturing faults; simulation based design verification; test generation; unified fault model; Circuit faults; Circuit simulation; Circuit testing; Hardware; Logic; Microprocessors; Pulp manufacturing; Random number generation; Test pattern generators; Workstations;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894247
