Self test architecture for testing complex memory structures

The structural complexity and test challenges of complex dependent memory structures are described. An isolation strategy to minimize the test logic overhead and delay penalty is presented. A set of custom memory test algorithms is designed to test the memory cell, bridging and multi-port faults in complex dependent memory structures. A novel programmable memory BIST architecture to realize the developed custom memory test algorithms has been described. The proposed memory BIST architecture can be used to test the dependent memory structures in different stages of their fabrication and assembly. The experimental results demonstrate the area overhead of different components of the proposed programmable memory BIST architecture