Title :
A programmable BIST architecture for clusters of multiple-port SRAMs
Author :
Benso, Alfredo ; Di Carlo, S. ; Di Natale, G. ; Prinetto, Olo ; Lobetti Bodoni, M.
Author_Institution :
Dipt. di Autom. e Inf., Politecnico di Torino, Italy
Abstract :
This paper presents a BIST architecture, based on a single microprogrammable BIST processor and a set of memory wrappers, designed to simplify the test of a system containing many distributed multi-port SRAMs of different sizes (number of bits, number of words), access protocol (asynchronous, synchronous), and timing
Keywords :
SRAM chips; built-in self test; fault diagnosis; integrated circuit testing; memory architecture; microprogramming; March algorithm; background pattern generator; fault diagnosis; memory architecture; memory wrappers; multiple-port SRAM clusters; programmable BIST architecture; single microprogrammable BIST processor; Access protocols; Automatic generation control; Built-in self-test; Communication networks; Memory management; Random access memory; Read-write memory; System testing; Test pattern generators; Timing;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894249
