Power pin testing: making the test coverage complete

Author

De Jong, Frans ; Kup, B. ; Schuttert, Rodger

Author_Institution

Philips Res., Netherlands

fYear

2000

fDate

2000

Firstpage

575

Lastpage

584

Abstract

Most modern ICs have multiple power and ground pins. It becomes necessary that all these pins are indeed connected to the board. In this paper a structural test method is presented for testing the connections of power and ground pins to the board. This on-chip test method is based on supply current detection between a bonding pad and its connection to the IC power distribution network. The method has been implemented and evaluated on a CMOS IC, using IEEE Std. 1149.1 to control and observe the embedded current sensors

Keywords

CMOS integrated circuits; VLSI; boundary scan testing; built-in self test; electric current measurement; integrated circuit testing; power supply circuits; production testing; BIST; CMOS IC; IC power distribution network; IEEE Std. 1149.1; VLSI; bonding pad; boundary scan cells; complete test coverage; embedded current sensors; ground pins; on-chip test method; pin connections; power pin testing; production IC; structural test method; supply current detection; voltage drop; Circuit faults; Circuit testing; Costs; Impedance; Inspection; Integrated circuit testing; Pins; Power supplies; Power systems; Production;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894251

Filename

894251