Integrated switchable inductors with symmetric differential layout

Author

Wang, Jia-Lun ; Tzeng, Yan-Ru ; Huang, Tzuen-Hsi

Author_Institution

Nat. Cheng Kung Univ., Tainan

fYear

2006

fDate

12-15 Dec. 2006

Firstpage

1369

Lastpage

1372

Abstract

An integrated switchable inductor with symmetric differential layout is proposed. It can be achieved over 50% area shrinkage as compared with the traditional ones. Three testkeys with a typical switch-ON inductance of about 2.1 nH (at 1.8 GHz) were pre-designed using an electromagnetic simulator and successfully verified by TSMC´s 0.18 mum RF CMOS technology. The measured ON/OFF inductance values are of 2.1 nH / 2.7 nH, 2.1 nH / 2.4 nH and 2.0 nH / 2.2 nH; and the Q-factors are of 4.1 / 6.2, 4.6 / 6.1 and 5.1 / 6.1, respectively. The Q-factor degradation of proposed switchable inductors due to the different inner turn size effect is discussed and a simple inductor lumped-circuit model is proposed with a relatively reasonable accuracy up to 10 GHz. A VCO testkey with the integration of such switchable inductor is also demonstrated.

Keywords

CMOS integrated circuits; Q-factor; inductance measurement; inductors; lumped parameter networks; voltage-controlled oscillators; Q-factors; TSMC RF CMOS technology; VCO testkey; electromagnetic simulator; inductance measurement; integrated switchable inductors; lumped-circuit model; size 0.18 mum; symmetric differential layout; CMOS technology; Degradation; Electromagnetic induction; Electromagnetic measurements; Inductance measurement; Inductors; Q factor; Radio frequency; Testing; Voltage-controlled oscillators; Switchable inductor; differential inductor; inductor lumped-circuit model; multi-standard VCO;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave Conference, 2006. APMC 2006. Asia-Pacific

Conference_Location

Yokohama

Print_ISBN

978-4-902339-08-6

Electronic_ISBN

978-4-902339-11-6

Type

conf

DOI

10.1109/APMC.2006.4429661

Filename

4429661