Author :
Stevens, Ken ; Ginosar, Ran ; Rotem, Shai
Author_Institution :
Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA
Abstract :
Relative Timing is introduced as an informal method for aggressive asynchronous design. It is demonstrated on three example circuits (C-Element, FIFO, and RAPPID Tag Unit), facilitating transformations from speed-independent circuits to burst-mode, relative timed, and pulse-mode circuits. Relative timing enables improved performance, area, power and testability in all three cases
Keywords :
VLSI; asynchronous circuits; delays; integrated circuit design; logic design; timing; C-Element; FIFO; RAPPID Tag Unit; aggressive asynchronous design; area; burst-mode; performance; pulse-mode circuits; relative timing; speed-independent circuits; testability; Asynchronous circuits; Circuit synthesis; Clocks; Delay effects; Delay estimation; Design automation; Design methodology; Radio access networks; Timing; Very large scale integration;
Conference_Titel :
Advanced Research in Asynchronous Circuits and Systems, 1999. Proceedings., Fifth International Symposium on
Conference_Location :
Barcelona
Print_ISBN :
0-7695-0031-5
DOI :
10.1109/ASYNC.1999.761535
