Digital serial communication device testing and its implications on automatic test equipment architecture

The rapid deployment of Gigabit differential signal I/O buffers in ASICs and other ICs for systems such as SONET, Firewire, Ethernet, and Fiber Channel is presenting several challenges for testing. At the present time, testing the functionality of these ICs can only be done by using expensive stand-alone bit-error-rate test sets. The excessive test time and cost makes this approach impossible for volume production. On the other hand, the industrial trend for higher level of integration means that Gigabit serial ports can be used as a standard I/O macro for any IC. There is an urgent need for Automatic Test Equipment (ATE) manufacturers to design multi-port, differential instruments and integrate them into test systems, including control software. In this article, as an extension to the challenges that we listed in the 1999 International Technology Roadmap for Semiconductors, we will discuss the impact on ATE architecture in order to accommodate multi-Gb/s serialcom tests, such as embedded clock recovery circuit testing, asynchronous testing, jitter generation/tolerance/transfer testing etc. We will describe what it takes to extend a conventional ATE´s capability for testing multiple Giga-bit-per-second (Gb/s) SerDes (Serializer/Deserializer), and how the throughput can be improved