Title :
An approach to testing 200 ps echo clock to output timing on the double data rate synchronous memory
Author :
Van Dinh, Dieu ; Rabitoy, Virginia
Author_Institution :
Semicond. Products Sector, Motorola Inc., Austin, TX, USA
Abstract :
This paper describes an approach to testing DDR echo clock outputs and transfer data specifications. Tester accuracy issues create difficulty in guaranteeing the 200 ps spec timing between these two groups of outputs. This approach will find the balance between accurate testing and test costs
Keywords :
SRAM chips; clocks; echo; integrated circuit testing; timing; 200 ps; data transfer; double data rate SRAM; echo clock testing; output timing; synchronous memory; Accuracy; Clocks; Constraint optimization; Costs; Frequency; Packaging; Production; Random access memory; Testing; Timing;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894255
