DocumentCode
2762933
Title
Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits
Author
Oakland, Steven F.
Author_Institution
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fYear
2000
fDate
2000
Firstpage
628
Lastpage
637
Abstract
This paper addresses four issues associated with using IEEE Standard 1149.1 on system-on-a-chip integrated circuits (SOC ICs). First, a new, simplified method for accessing debug registers in processor cores embedded within ICs is presented. Second, structural information required by hardware/software processor development tools is presented. Third, issues associated with boundary-scan description language (BSDL) are discussed. Finally, high-speed boundary-scan cells that avoid a multiplexer delay are presented
Keywords
IEEE standards; boundary scan testing; integrated circuit testing; microprocessor chips; IEEE 1149.1 standard; boundary-scan description language; debug register; embedded processor core; high-speed boundary-scan cell; structural testing; system-on-a-chip integrated circuit; Clocks; Delay; Logic testing; Microelectronics; Multiplexing; Object recognition; Pins; Shift registers; System-on-a-chip; USA Councils;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894257
Filename
894257
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