DocumentCode
2762975
Title
Comparison of DSP and FPGA realization of neural speed estimator for 2-mass system
Author
Kaminski, Marcin ; Orlowska-Kowalska, Teresa
Author_Institution
Inst. of Electr. Machines, Drives & Meas., Wroclaw Univ. of Technol., Wroclaw, Poland
fYear
2011
fDate
27-30 June 2011
Firstpage
1543
Lastpage
1548
Abstract
In this paper two hardware applications of neural state estimator for the two-mass drive system are presented. One of them is realized in a Digital Signal Processor (DSP), and the second consists in parallel implementation of neural networks in a reconfigurable Field-Programmable Gate Array (FPGA) placed in CompactRIO controller. Described solutions of neural network implementations are used for the estimation of the load-side speed of an electrical drive with elastic joint. Several design and programming problems are presented. Developed neural estimators are tested in the laboratory drive. Application of the neural network with FPGA gives better results, especially on drive system transients. Obtained results show high accuracy of the load speed estimation with the presented neural estimator. High precision of calculation is also obtained in the presence of the load time constant changes.
Keywords
digital signal processing chips; electric drives; field programmable gate arrays; neurocontrollers; CompactRIO controller; DSP; FPGA; digital signal processor; drive system transients; elastic joint; electrical drive; field-programmable gate array; load speed estimation; neural speed estimator; two-mass drive system; Artificial neural networks; Digital signal processing; Estimation; Field programmable gate arrays; Hardware; Training; Transient analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Industrial Electronics (ISIE), 2011 IEEE International Symposium on
Conference_Location
Gdansk
ISSN
Pending
Print_ISBN
978-1-4244-9310-4
Electronic_ISBN
Pending
Type
conf
DOI
10.1109/ISIE.2011.5984390
Filename
5984390
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