Design and implementation of the digital controller for boost converter based on FPGA

Taking advantage of FPGA´s attractive features, this paper presents an improved digital pulse-width-modulator (DPWM) based sliding-mode controller (SMC) for boost converter that effectively alleviates the quantization effects. The dithering Multi-stAge-noise-SHaping (MASH) DPWM is introduced exhibiting a better idle tone suppression effect that achieves relatively higher effective number of bit (ENOB). The Linear Feedback Shift Register (LFSR) replaces the cumbersome pseudo-random generator as the dither generation module that is proven to be more effective. The SMC with the proper sliding coefficients aiming at a better dynamic response than the traditional PID controller cooperates with our proposed DPWM. Two individual boards, an analog-to-digital converter (ADC) and a boost converter, connecting to a Virtex-II FPGA platform compose a close-loop test environment. Experimental results verify the switching-mode-power-supply (SMPS) close-loop operation at 1MHz switching frequency with an 11-bit effective DPWM resolution.