Low power BIST design by hypergraph partitioning: methodology and architectures

Power consumption of digital systems may increase significantly during testing. In this paper, we propose a novel low power/energy Built-in Self Test (BIST) strategy based on circuit partitioning. The strategy consists of partitioning the original circuit into structural subcircuits so that each subcircuit can be successively tested through different BIST sessions. In partitioning the circuit and planning the test session, the switching activity in a time interval (i.e. The average power) as well as the peak power consumption are minimized. Moreover, the total energy consumption during BIST is also reduced since the test length required to test the subcircuits is not so far from the test length for the original circuit. The proposed strategy can be applied to either test-per-scan or test-per-clock BIST schemes by slightly modifying conventional TPG structures as illustrated in this paper. Results on ISCAS circuits show that average power reduction of up to 62%, peak power reduction of up to 57%, and energy reduction of up to 82% can be achieved at a very low area cost in terms of area overhead and with almost no penalty on the circuit timing