Title :
An efficient and reconfigurable architecture for RC5
Author :
Li, Hua ; Li, Jianzhou ; Yang, Jing
Author_Institution :
Dept. of Math. & Comput. Sci., Lethbridge Univ., Alta.
Abstract :
RC5 is a widely used symmetric block cipher which has a variable word size, number of rounds, and length of secret key. In this paper, we propose an efficient and reconfigurable hardware architecture for the RC5 block cipher implementation. The design can be reconfigured according to the different application requirements with variable parameters. It is simulated in Verilog HDL and implemented on Xilinx FPGA. Comparison shows that it has high throughput and low hardware complexity
Keywords :
field programmable gate arrays; hardware description languages; reconfigurable architectures; RC5 reconfigurable architecture; Verilog HDL; Xilinx FPGA; hardware complexity; reconfigurable hardware architecture; symmetric block cipher; variable word size; Computer architecture; Computer science; Cryptography; Data security; Field programmable gate arrays; Hardware design languages; Mathematics; Reconfigurable architectures; Throughput; Wireless communication;
Conference_Titel :
Electrical and Computer Engineering, 2005. Canadian Conference on
Conference_Location :
Saskatoon, Sask.
Print_ISBN :
0-7803-8885-2
DOI :
10.1109/CCECE.2005.1557299
