Title :
System issues in boundary-scan board test
Author :
Parker, Kenneth P.
Author_Institution :
Manuf. Test Div, Agilent Technol., Loveland, CO, USA
Abstract :
Boards have evolved into complex systems and even collections of interacting systems. Test engineers struggle to find out how these systems are initialized and booted because of poor documentation. While boundary-scan (IEEE Std 1149.1) is a powerful test tool, test engineers are finding out that yesterday´s DFT rules and test approaches may actually be detrimental to successfully testing systems on a board. One culprit is the boot up process of the board and even individual ICs. The author attempts to answer the question of what can be done to address this
Keywords :
IEEE standards; automatic testing; boundary scan testing; design for testability; field programmable gate arrays; integrated circuit testing; DFT rules; FPGA; IEEE Std 1149.1; boot up process; boundary-scan board test; crypto-clock domains; system issues; test strategy; Circuit testing; Clocks; Field programmable gate arrays; Integrated circuit testing; Manufacturing; Oscillators; Power engineering and energy; System testing; Systems engineering and theory; USA Councils;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894268
