Title :
A scalable and efficient methodology to extract two node bridges from large industrial circuits
Author :
Zachariah, Sujit T. ; Chakravarty, Sreejit
Author_Institution :
Archit. Group, Intel Corp., Santa Clara, CA, USA
Abstract :
Enumeration and prioritization of highly probable bridges based on the circuit layout and manufacturing defect data is a key step in defect based testing. Existing solutions either do not scale to large designs or compromise on the accuracy of the computation when applied to very large circuits. This paper presents a scalable and efficient methodology to accurately extract two node bridges from very large circuits. To our knowledge, this is the first solution to be presented that can process such large industrial designs accurately. It also naturally addresses two important issues viz. through the cell routing and name propagation. Experimental results illustrating key features of the algorithm, including scalability and efficient memory usage, are presented
Keywords :
VLSI; circuit layout CAD; divide and conquer methods; fault simulation; integrated circuit layout; integrated circuit testing; circuit layout; defect based testing; divide and conquer approach; efficient memory usage; fault model; high level flow chart; inductive fault analysis; large industrial circuits; manufacturing defect data; name propagation; net equivalencies at boundaries; scalable efficient methodology; segment fault lists generation; through the cell routing; two node bridges extraction; weighted critical area; Bridge circuits; Circuit faults; Circuit testing; Data analysis; Data mining; Databases; Fault diagnosis; Manufacturing industries; Routing; Scalability;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894271