Title :
Thick-Strained-Si/SiGe CMOS Technology with Selective-Epitaxial-Si Shallow-Trench Isolation (SES-STI)
Author :
Miyamoto, M. ; Sugii, N. ; Yoshida, Y. ; Hoshino, Y. ; Kimura, Y. ; Kondo, M. ; Ohnishr, K.
Author_Institution :
Micro Device Div., Hitachi Ltd., Tokyo
Abstract :
We developed a new bulk strained-Si/SiGe CMOS technology free from any Ge-related problems, which has a 90-110-nm strained-Si layer thicker than the limit at which misfit-dislocations occur, and a new shallow-trench isolation structure that has a selective-epitaxial Si layer to cover up the SiGe trench surface. This process has advantages in manufacturing compatibility with Si-CMOS process, low junction leakage current, and no reliability problems caused by Ge out-diffusion, with the same performance enhancement as thin (< 20 nm) strained-Si/SiGe
Keywords :
CMOS integrated circuits; Ge-Si alloys; elemental semiconductors; epitaxial growth; integrated circuit reliability; isolation technology; silicon; 90 to 110 nm; CMOS technology; Si-SiGe; leakage current; manufacturing compatibility; misfit-dislocations occur; selective-epitaxial layer; shallow-trench isolation; trench surface; CMOS technology; Capacitive sensors; Charge carrier processes; Etching; Germanium silicon alloys; Isolation technology; Leakage current; Oxidation; Silicon germanium; Surface cleaning;
Conference_Titel :
SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International
Conference_Location :
Princeton, NJ
Print_ISBN :
1-4244-0461-4
DOI :
10.1109/ISTDM.2006.246572
