DocumentCode
2763352
Title
A mixed mode BIST scheme based on reseeding of folding counters
Author
Hellebrand, Sybille ; Liang, Hua-Guo ; Wunderlich, Hans-Joachim
Author_Institution
Innsbruck Univ., Austria
fYear
2000
fDate
2000
Firstpage
778
Lastpage
784
Abstract
In this paper a new scheme for deterministic and mixed mode scan-based BIST is presented. It relies on a new type of test pattern generator which resembles a programmable Johnson counter and is called folding counter. Both the theoretical background and practical algorithms are presented to characterize a set of deterministic test cubes by a reasonably small number of seeds for a folding counter. Combined with classical approaches for test width compression and with pseudorandom pattern generation these new techniques provide an efficient and flexible solution for scan-based BIST. Experimental results show that the proposed scheme outperforms previously published approaches based on the reseeding of LFSRs or Johnson counters
Keywords
automatic test pattern generation; built-in self test; integrated circuit testing; logic testing; complex SoC; deterministic BIST; deterministic test cubes; mixed mode BIST scheme; programmable Johnson counter; pseudorandom pattern generation; reseeding of folding counters; scan-based BIST; test pattern generator; test width compression; Built-in self-test; Circuit faults; Circuit testing; Counting circuits; Hardware; Integrated circuit testing; Switches; System testing; System-on-a-chip; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894274
Filename
894274
Link To Document