Novel technique for built-in self-test of FPGA interconnects

Author

Sun, Xiaoling ; Xu, Jian ; Ben Chan ; Trouborst, Pieter

Author_Institution

Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada

fYear

2000

fDate

2000

Firstpage

795

Lastpage

803

Abstract

This paper presents the first BIST approach for testing interconnects of SRAM-based FPGAs using error control coding. The proposed scheme requires a total of six test configurations and has superior multiple fault coverage on wire segment stuck-at, stuck-open and bridging faults, programmable switch stuck on/off faults, and the combinations of these faults in global routing resources

Keywords

SRAM chips; built-in self test; fault simulation; field programmable gate arrays; integrated circuit interconnections; integrated circuit testing; logic partitioning; logic testing; FPGA interconnects; SRAM-based FPGA; bridging faults; built-in self-test; error control coding; fault models; global routing resources; multiple fault coverage; partitioning; programmable switch stuck on/off faults; stuck-open faults; test configurations; wire segment stuck-at faults; Built-in self-test; Circuit faults; Circuit testing; Error correction; Field programmable gate arrays; Integrated circuit interconnections; Pins; Routing; Switches; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894276

Filename

894276