Different experiments in test generation for XILINX FPGAs

Author

Renovell, M. ; Zorian, Y.

Author_Institution

LIRMM, Montpellier, France

fYear

2000

fDate

2000

Firstpage

854

Lastpage

862

Abstract

In this paper, we describe an experiment about structural testing of two XILINX FPGAs families. In our practical approach, the FPGA is divided into different arrays: an array of logic cells, an array of interconnect cells and an array of RAM cells. For each part, we use a specific fault model and we generate test configurations and test vectors for the considered models. In each case, for each array, we try to minimize as much as possible the number of test configurations because re-programming FPGAs is really time consuming

Keywords

automatic testing; fault diagnosis; field programmable gate arrays; integrated circuit testing; integrated memory circuits; logic testing; minimisation; random-access storage; software reusability; RAM cells arrays; XILINX FPGA; fault model; interconnect cells arrays; logic cells arrays; minimisation; re-programming; structural testing; test configurations; test generation; test vectors; time consumption; Application specific integrated circuits; Circuit testing; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic circuits; Logic design; Logic testing; Programmable logic arrays; Read-write memory;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894292

Filename

894292