Title :
Adapting scan architectures for low power operation
Author_Institution :
Texas Instrum. Inc., USA
Abstract :
Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture
Keywords :
built-in self test; delays; integrated circuit testing; logic design; logic testing; power supply circuits; BIST; adapted scan architecture; delay test; digital circuitry; low power mode; low power operation; parallel scan architecture; pre-adapted scan architectures; scan architectures; scan path adaptation; Batteries; Built-in self-test; Circuit testing; Computer architecture; Digital signal processing; Integrated circuit testing; Logic circuits; Logic testing; Packaging; Wafer scale integration;
Conference_Titel :
Test Conference, 2000. Proceedings. International
Conference_Location :
Atlantic City, NJ
Print_ISBN :
0-7803-6546-1
DOI :
10.1109/TEST.2000.894297
