Optimization trade-offs for vector volume and test power

In today´s large designs, especially large SOC (system-on-a-chip) designs, vector volume for a single core could dominate the memory resources of the target tester and leave little or no room for other vectors. To this end, delivery of an “optimized” or “reduced” vector set, without any loss of coverage, is preferred. One commercial means of delivering an optimized vector set is to compress the vectors during vector generation. Another applicable solutions to understand the overlapping faults among various fault models and remove them from the fault lists for certain pattern types. The main problem with these optimization approaches is that compressed vectors create more switching activities, which could potentially cause average power dissipation, instantaneous and peak power during test to be significantly higher than normal operation. Test power is such a big concern in large SOC designs that the power associated with the “reuse” vectors must be understood. This paper presents a case study of a Motorola Version 3 ColdFire(R) microprocessor core, with a focus on the various vector optimizations and their ramifications on test power