DocumentCode
2763727
Title
An ILP formulation to optimize test access mechanism in system-on-chip testing
Author
Nourani, Mehrdad ; Papachristou, Christos
Author_Institution
Center for Integrated Circuits & Syst., Texas Univ., Dallas, TX, USA
fYear
2000
fDate
2000
Firstpage
902
Lastpage
910
Abstract
We present an optimization method that complies with IEEE P1500 draft standard and deals with modeling and design of the test access mechanism for the SoCs. The basic goal is to develop a global design for the test methodology and optimization technique for testing a core-based SoC in its entirety. We propose an ILP formulation to minimize the hardware cost or the overall access time which also produces the test access schedule
Keywords
circuit CAD; circuit optimisation; design for testability; digital integrated circuits; integer programming; integrated circuit testing; linear programming; IEEE P1500 draft standard; core-based SoC; global design; optimization method; system-on-chip testing; test access mechanism; test methodology; Circuit testing; Control systems; Costs; Design methodology; Integrated circuit modeling; Integrated circuit testing; Optimization methods; System testing; System-on-a-chip; Time to market;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2000. Proceedings. International
Conference_Location
Atlantic City, NJ
ISSN
1089-3539
Print_ISBN
0-7803-6546-1
Type
conf
DOI
10.1109/TEST.2000.894301
Filename
894301
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