Deception by design: fooling ourselves with gate-level models

The distortion of test coverage statistics by overly simplistic circuit and fault models is explored. It is shown that the artificially high single stuck-at coverage reported on traditional gate-level models results in the omission of test patterns essential to achieve full coverage. The problem lies not directly with the fault model, but instead with the gate models and test generator assumptions used. The necessity of two-pattern tests is demonstrated on simple library cells, and the stuck-at coverage improvement measured on benchmark circuits is shown to average 33%. The need for a superior fault model is explained