Register-transfer level fault modeling and test evaluation techniques for VLSI circuits

Stratified fault sampling is used in RTL fault simulation to estimate the gate-level fault coverage of given test patterns. RTL fault modeling and fault injection algorithm are developed such that the RTL fault list of a module can be treated as a representative fault sample of the collapsed stuck-at fault set of the module. The RTL coverage for the module is experimentally found to track the gate-level coverage within the statistical error bounds. For a VLSI system, consisting of several modules, the overall coverage is a weighted sum of RTL module coverages. Several techniques are proposed to determine these weights, known as stratum weights. For a system timing controller ASIC, the stratified RTL coverage of verification test-benches was estimated within 0.6% of the actual gate-level coverage. This ASIC consists of 40 modules (9,000 lines of Verilog HDL) that are synthesized into 17,126 equivalent logic gates by a commercial synthesis tool. Similar results on two other VLSI systems are reported