Technique for testing a very high speed mixed signal read channel design

PRML (partial response maximum likelihood) read channel devices are heterogeneous, complex, mixed signal devices. This paper describes methodology for testing a state-of-the-art CMOS read channel, including design-for-test (DFT) techniques, device-interface-board (DIB) design features and test flow. DFT techniques such as scan, built-in self-test (BIST) loop-back and ad-hoc analog test features are discussed. Analog test grading methods (test-for-quality) are also presented. Afterwards a brief overview of the DIB hardware highlighting critical features such as wide band analog and high speed digital undersampling tester interfaces are reviewed. An overview of the test suite defining the mix of functional, structured, IDDQ and BIST tests is offered. The problems and possible solutions of embedding a PRML channel into a system-on-chip are also extensively explored