Structural test in a board self test environment

Author

Pillkahn, Ulf

Author_Institution

Siemens AG, Munich, Germany

fYear

2000

fDate

2000

Firstpage

1005

Lastpage

1012

Abstract

In this paper, a novel technique for the verification of board level connections on PCBs is presented. The time domain method is used to identify whether a pin connection is faulty or not. The test pulse and evaluation circuitry are part of the chip. Although the chip size increases slightly, the method is highly efficient. No ATE is necessary to carry out the test and since only the physical behaviour of the connection from the internal driver via pin to board is examined, no test vectors are needed. The test time and the test preparation time are lower compared with conventional test methods

Keywords

automatic testing; boundary scan testing; built-in self test; printed circuit testing; soldering; time-domain reflectometry; PCB; board level connections verification; board self test environment; boundary scan; fault models; impulse response generation; interconnect test; internal driver; physical behaviour; pin connection; pin to board; solder connections; structural test; test time; time domain method; time domain reflectometry; Automatic testing; Circuit faults; Circuit testing; Controllability; Flyback transformers; Integrated circuit interconnections; Integrated circuit technology; Integrated circuit testing; Logic testing; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2000. Proceedings. International

Conference_Location

Atlantic City, NJ

ISSN

1089-3539

Print_ISBN

0-7803-6546-1

Type

conf

DOI

10.1109/TEST.2000.894313

Filename

894313