DocumentCode :
2763981
Title :
Area-efficient parallel white Gaussian noise generator
Author :
Alimohammad, Amirhossein ; Cockburn, Bruce F. ; Schlegel, Christian
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
fYear :
2005
fDate :
1-4 May 2005
Firstpage :
1872
Lastpage :
1875
Abstract :
We propose an area-efficient field-programmable gate array (FPGA) implementation of a Gaussian noise generator (GNG) that is based on the Box-Muller algorithm. The compact GNG can be realized on the same FPGA chip as the circuit under test to allow digital communication systems to be accurately characterized. An efficient implementation of a pseudo-random number generator is utilized that reduces FPGA resource utilization. Also, on-chip block memory is used efficiently to improve the noise quality. The implemented design on a Xilinx XC2V4000-6 FPGA utilizes only 3% of the configurable resources and operates at up to 165 MHz. The parallel, configurable and scalable datapath of the GNG offers trade-offs between sampling rate and area
Keywords :
Gaussian noise; field programmable gate arrays; noise generators; random number generation; white noise; Box-Muller algorithm; FPGA chip; Xilinx XC2V4000-6 FPGA; a pseudo-random number generator; digital communication systems; field-programmable gate array; noise quality; on-chip block memory; resource utilization; white Gaussian noise generator; Bit error rate; Character generation; Circuit testing; Digital communication; Field programmable gate arrays; Gaussian noise; Noise generators; Random variables; Signal generators; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical and Computer Engineering, 2005. Canadian Conference on
Conference_Location :
Saskatoon, Sask.
ISSN :
0840-7789
Print_ISBN :
0-7803-8885-2
Type :
conf
DOI :
10.1109/CCECE.2005.1557347
Filename :
1557347
Link To Document :
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