Title :
All-digital PLL with ΔΣ DLL embedded TDC
Author :
Han, Yi ; Lin, Dongyang ; Geng, Shuli ; Xu, Ningsheng ; Rhee, Woogeun ; Oh, Tae-Young ; Wang, Zhen
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
An all-digital PLL (ADPLL) which employs a ΔΣ delay-locked loop (DLL) to achieve a PVT-insensitive time resolution of the time-to-digital converter (TDC) as well as noise-shaped dithering is implemented in 65 nm CMOS. Experimental results show that the proposed method can achieve spur reduction with slight degradation of in-band phase noise. The 1.8 GHz ADPLL consumes 14.3 mW, while the TDC with the ΔΣ DLL consumes 2.1 mW.
Keywords :
CMOS integrated circuits; delay lock loops; phase locked loops; time-digital conversion; ΔΣ DLL embedded TDC; ΔΣ delay-locked loop; CMOS; all-digital PLL; frequency 1.8 GHz; in-band phase noise; noise-shaped dithering; power 14.3 mW; power 2.1 mW; size 65 nm; time-to-digital converter;
Journal_Title :
Electronics Letters
DOI :
10.1049/el.2012.3017
