Multiple-parameter CMOS IC testing with increased sensitivity for I DDQ

Technology scaling challenges the effectiveness of current-based test techniques such as I_DDQ. Furthermore, existing leakage reduction techniques are not as effective in aggressively scaled technologies. We exploited intrinsic dependencies of transistor and circuit leakage on clock frequency, temperature, and reverse body bias (RBB) to discriminate fast ICs from defective ones. Transistor and circuit parameters were measured and correlated to demonstrate leakage-based testing solutions with improved sensitivity. We used a test IC with available body terminals for our experimental measurements. Our data suggest adopting a sensitive multiple-parameter test solution. For high performance IC applications, we propose a new test technique, I _DDQ versus F_MAX (maximum operating frequency), in conjunction with using temperature (or RBB) to improve the defect detection sensitivity. For cost sensitive applications, I_DDQ versus temperature test can be deployed. Our data show that temperature (cooling from 110°C to room) improved sensitivity of I_DDQ Versus F_MAX two-parameter test by more than an order of magnitude (13.8X). The sensitivity can also be tuned by proper selection of a temperature range to match a required DPM level