Title :
Occurrence and elimination of anomalous temperature dependence of latchup trigger currents in BiCMOS processes
Author :
Ooms, Eric R. ; Van der Pol, Jacob A.
Author_Institution :
Q&R Dept. of Consumer Syst., Philips Semicond., Nijmegen, Netherlands
Abstract :
Latchup trigger currents in a BiCMOS process show an extreme temperature dependence (from >100 mA to <3 mA with ΔT=1°C), severely affecting product latchup susceptibility. The effect is strongly process and wafer fab dependent and caused by lifting of the substrate potential, primarily due to saturation of bipolar transistors, causing hole injection and subsequent turn-on of parasitic n-type field transistors. The effect can be eliminated by a combination of process and design measures. The use of a buried-P layer or of low ohmic (⩽1 Ωcm) substrates is especially effective. For qualification purposes, a 30°C test temperature guard-banding is needed to take the effect into account
Keywords :
BiCMOS integrated circuits; buried layers; fault currents; integrated circuit manufacture; integrated circuit reliability; integrated circuit technology; thermal analysis; 1 ohmcm; 100 mA; 3 mA; BiCMOS process; BiCMOS processes; bipolar transistor saturation; buried-P layer; design measures; hole injection; latchup trigger currents; low ohmic substrates; parasitic n-type field transistors; process dependent effect; process measures; product latchup susceptibility; qualification; substrate potential; temperature dependence; test temperature guard-banding; wafer fab dependent effect; BiCMOS integrated circuits; Bipolar transistor circuits; Bipolar transistors; CMOS process; Qualifications; Stress; Substrates; Temperature dependence; Testing; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5220-3
DOI :
10.1109/RELPHY.1999.761605
