• DocumentCode
    2764160
  • Title

    Investigation of Geometry Scaling Effect on Si BJT and SiGe HBT fabricated on SOI Substrates

  • Author

    Liao, S.H. ; Chang, S.T. ; Lin, Colin Yu

  • fYear
    2006
  • fDate
    15-17 May 2006
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper, the key design device parameter of SOI such as the buried oxide thickness, lateral scaling, and thermal effect are studied by 2D device simulator DESSIStrade
  • Keywords
    Ge-Si alloys; heterojunction bipolar transistors; silicon-on-insulator; 2D device simulator; DESSIS; SOI substrates; Si BJT; SiGe; SiGe HBT; buried oxide thickness; geometry scaling effect; heterojunction bipolar transistor; thermal effect; BiCMOS integrated circuits; Breakdown voltage; Doping; Geometry; Germanium silicon alloys; Heterojunction bipolar transistors; Physics; RF signals; Radio frequency; Silicon germanium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SiGe Technology and Device Meeting, 2006. ISTDM 2006. Third International
  • Conference_Location
    Princeton, NJ
  • Print_ISBN
    1-4244-0461-4
  • Type

    conf

  • DOI
    10.1109/ISTDM.2006.246491
  • Filename
    1715985
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2764160