Title :
Analysis of snapback behavior on the ESD capability of sub-0.20 μm NMOS
Author :
Amerasekera, Ajith ; Gupta, Vikas ; Vasanth, Karthik ; Ramaswamy, Sridhar
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The self-biased lateral NPN (LNPN) operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined. The effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 μm, 0.18 μm, and 0.25 μm. Specifically, the influence of gate oxides <30 Å, and the effects of CoSi2 and TiSi2 are characterized with the purpose of defining process dependencies and design space. It is shown that as gate oxides get thinner, oxide breakdown may become a limiting factor depending on the LNPN properties. Furthermore, changes in LNPN current gain through process or design variations, and the substrate resistance, can be used to tune ESD performance. Hence, transistor design and process choices can be made to ensure that the LNPN is optimized for successful operation even for very thin gate oxides in sub-0.2 μm technologies
Keywords :
MOSFET; dielectric thin films; electric current; electrostatic discharge; optimisation; protection; semiconductor device metallisation; semiconductor device models; semiconductor device testing; 0.13 micron; 0.18 micron; 0.2 micron; 0.25 micron; 30 angstrom; CoSi2 effects; CoSi2-SiO2-Si; ESD capability; ESD performance; LNPN behavior; LNPN current gain; LNPN operation; LNPN optimization; LNPN properties; NMOSFETs; TiSi2 effects; TiSi2-SiO2-Si; design space; design variations; device scaling; device simulations; feature sizes; gate oxide thickness; gate oxides; injection currents; oxide breakdown; process dependencies; process design; process variations; self-biased lateral NPN operation; snapback behavior; substrate resistance; transistor design; transistor process; Analytical models; Electric breakdown; Electrostatic discharge; MOS devices; MOSFETs; Process design; Protection; Space technology; Thermal resistance; Voltage;
Conference_Titel :
Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5220-3
DOI :
10.1109/RELPHY.1999.761608
