Title :
The use of a WLR technique to characterize voiding in 0.25 and 0.18 μm technologies for integrated circuits
Author :
Marathe, Amit ; Besser, Paul ; Tsiang, Jerry ; Tran, Khanh ; Pham, Vu ; Tracy, Bryan ; Fang, Peng
Author_Institution :
Technol. Dev. Group, Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
A quantitative correlation has been successfully demonstrated between the isothermal wafer level test results and severity of voiding in sub-micron interconnect lines. Isothermal test T50% and T 0.1% decrease while sigma increases, as the voiding becomes more severe. The isothermal wafer level test gives a good signal to indicate a significant decrease in severity of voiding with an anneal after metal etch and when a TiN underlayer is present in the metal stack. The isothermal test is thus shown to be a useful reliability tool for process monitoring and void detection in VLSI interconnects
Keywords :
VLSI; chemical interdiffusion; diffusion barriers; electromigration; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; process monitoring; thermal stresses; voids (solid); 0.18 micron; 0.25 micron; TiN; TiN underlayer; VLSI interconnects; WLR technique; anneal; integrated circuits; interconnect lines; isothermal test; isothermal test temperatures; isothermal wafer level test; metal etch; metal stack; process monitoring; quantitative correlation; reliability tool; void detection; voiding; voiding severity; wafer level reliability technique; Annealing; Circuit testing; Electromigration; Integrated circuit interconnections; Integrated circuit reliability; Integrated circuit technology; Isothermal processes; Metallization; Stress; Tin;
Conference_Titel :
Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5220-3
DOI :
10.1109/RELPHY.1999.761628
