A new pipeline design for binarization and thinning of fingerprint images

Author

Kheiri, Farshad ; Samavi, Shadrokh ; Karimi, Nader

Author_Institution

Dept. of Electr. & Comput., Isfahan Univ. of Technol.

fYear

2005

fDate

1-4 May 2005

Firstpage

2013

Lastpage

2016

Abstract

Two critical steps in fingerprint recognition are binarization and thinning of the image. The need for real-time processing led us to local adaptive thresholding approach for the binarization step. We introduce a new hardware for this purpose based on pipeline architecture. We propose a method for selecting an optimal block size for the thresholding purpose and then the binarized image is dilated. We also present a new pipeline structure for implementing the thinning algorithm. The suggested structure was implemented using Vertix II FPGAs from Xilinx Corporation. The processing time for a 572*572 image is about 1.45 milliseconds

Keywords

field programmable gate arrays; image recognition; image thinning; pipeline arithmetic; Vertix II FPGA; Xilinx Corporation; fingerprint image recognition; image binarization; local adaptive thresholding approach; optimal block size; pipeline architecture; real-time processing; thinning algorithm; Equations; Field programmable gate arrays; Fingerprint recognition; Gray-scale; Hardware; Image enhancement; Image matching; Pipelines; Pixel; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2005. Canadian Conference on

Conference_Location

Saskatoon, Sask.

ISSN

0840-7789

Print_ISBN

0-7803-8885-2

Type

conf

DOI

10.1109/CCECE.2005.1557380

Filename

1557380