Selective Epitaxial Si/SiGe for VT Shift Adjustment in High k pMOS Devices

This work discusses the influence of the underlying SiGe on the growth kinetics during the deposition of the Si-cap layer. The importance and feasibility of the required process control is demonstrated by charge pumping measurements and energy dispersive X-ray spectroscopy (EDX) on pMOS devices. The analysis clearly demonstrates the influence of the Si thickness on the quality of the gate dielectric/channel interface. We also discuss the presence of thermal loading effects, by comparing the growth behavior with and without Si recess prior to the SEG