A new experimental approach to evaluate plasma damage in nMOS and pMOS devices

Plasma treatments during IC processing steps are necessary for continuing CMOS dimensional scaling, lowering of the thermal budget and increasing the number of interconnect levels. During plasma processes, two major effects play a key role in reliability degradation: plasma nonuniformity and plasma radiation damage. The plasma nonuniformity and its associated high electric fields may easily induce electrical stress in the gate oxide, causing serious oxide charging and reliability degradation. Furthermore, the plasma damage strongly depends on gate interconnect topographies, device position on wafer, plasma characteristics and processing equipment. The plasma-induced high energy photons and particle bombardment may easily break bonds or induce current flow damage due to photo-injection, further increasing the device degradation. During the post metallisation annealing step, the oxide damage can be completely passivated, but not healed. In fact, the plasma damage may be easily reactivated by subsequent electrical stress, appearing as an anomalous oxide trapped charge. In this work, we have developed a stress and characterisation method suitable to precisely evaluate the plasma damage on fully processed nMOS and pMOS devices. The optimal stress conditions have been chosen to minimise both stress time and stress-induced damage. Wafer mapping capabilities of this technique have been demonstrated