Low voltage stress-induced-leakage-current in ultrathin gate oxides

Author

Nicollian, Paul E. ; Rodder, Mark ; Grider, Douglas T. ; Chen, Peijun ; Wallace, Robert M. ; Hattangady, Sunil V.

Author_Institution

Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA

fYear

1999

fDate

1999

Firstpage

400

Lastpage

404

Abstract

Stress-induced-leakage-current (SILC) is an important concern in ultrathin gate oxides because it may impose constraints on dielectric thickness scaling. We show that for oxides less than ~3.5 nm thick, interfacial traps generated from direct tunneling stress result in a sense voltage dependent SILC mechanism that can dominate the gate leakage current at low operating voltages

Keywords

CMOS integrated circuits; MOS capacitors; dielectric thin films; electron traps; high field effects; hole traps; integrated circuit testing; interface states; leakage currents; tunnelling; 3.5 nm; CMOS process; MOS capacitors; MOSFET; SILC; SiO₂-Si; dielectric thickness scaling; direct tunneling stress; gate leakage current; interfacial traps; low voltage stress-induced-leakage-current; operating voltages; oxide thickness; sense voltage dependent SILC mechanism; ultrathin gate oxides; Anodes; Capacitance-voltage characteristics; DC generators; Degradation; Leakage current; Low voltage; MOS devices; MOSFET circuits; Thermal stresses; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Reliability Physics Symposium Proceedings, 1999. 37th Annual. 1999 IEEE International

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5220-3

Type

conf

DOI

10.1109/RELPHY.1999.761646

Filename

761646