A New Architecture of UHF RFID Digital Receiver for SoC Implementation

Author

Huang, Chenling ; Liu, Yuan ; Han, Yifeng ; Min, Hao

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ.

fYear

2007

fDate

11-15 March 2007

Firstpage

1659

Lastpage

1663

Abstract

A new architecture of UHF (ultra high frequency) RFID (radio frequency identification) digital receiver for SoC (system-on-chip) implementation is presented in this paper. For the system requirements, the design uses a unique two-stage correlation algorithm to estimate the frequency of the received data which may have large frequency deviation and also to achieve fast data decoding. Considering the single chip integration, we optimize the implementation for both low hardware cost and quick response. The function of the design is verified through FPGA implementation on Altera StratixII EP2S60 with great performance and its chip design used the SMIC 0.18mum process along with other parts of the UHF RFID interrogator chip.

Keywords

UHF integrated circuits; field programmable gate arrays; radio receivers; radiofrequency identification; system-on-chip; 0.18 micron; FPGA implementation; SoC implementation; UHF RFID digital receiver; UHF RFID interrogator chip; data decoding; system-on-chip implementation; two-stage correlation algorithm; ultra high frequency radio frequency identification digital receiver; Algorithm design and analysis; Chip scale packaging; Cost function; Decoding; Field programmable gate arrays; Frequency estimation; Hardware; Radiofrequency identification; Receivers; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Wireless Communications and Networking Conference, 2007.WCNC 2007. IEEE

Conference_Location

Kowloon

ISSN

1525-3511

Print_ISBN

1-4244-0658-7

Electronic_ISBN

1525-3511

Type

conf

DOI

10.1109/WCNC.2007.312

Filename

4224557